First, a related-art semiconductor device is described. FIG. 2 is a plan view of the related-art semiconductor device.
In general, an NMOS transistor is used for an ESD protection circuit for protecting an internal circuit from ESD. The pattern of the NMOS transistor is laid out as illustrated in FIG. 2, for example.
The NMOS transistor includes a plurality of sources 5 and a plurality of drains 4 that are alternately formed, a plurality of even-numbered channels formed between the sources 5 and the drains 4, a plurality of gates 3 formed above the plurality of channels, back gates 1a formed adjacent to outermost sources 5 among the plurality of sources 5, a back gate 1b buried in the other sources 5, and a back gate 1c formed so as to surround the NMOS transistor (see, for example, Patent Literature 1).